1. Field of the Invention
This invention relates generally to keeper circuits, and more particularly to adaptive keeper transistor sizing for dynamic circuits based on global process corner data.
2. Description of the Related Art
Conventionally, keeper circuits have been utilized in dynamic circuits to prevent leaking at an internal dynamic node. For example, dynamic wide OR circuits commonly utilized in large register files often use keeper circuits to prevent unintentional discharging of the internal dynamic node, as illustrated in FIG. 1.
FIG. 1 is a schematic diagram showing a conventional dynamic wide OR circuit 100. The dynamic wide OR circuit 100 includes a precharge p-channel transistor 102, having a first terminal coupled to VDD, a second terminal coupled to an internal dynamic node 110, and a gate coupled to a clock signal 108. In addition, a plurality of evaluation transistors 104a-104c is included in the dynamic wide OR circuit 100. Each evaluation transistor 104a-104c includes a first terminal coupled to the internal dynamic node 110 and a second terminal coupled to a first terminal of transistor 106. In addition, the gate of each evaluation transistor 104a-104c is coupled to an input In0, In1, and In2, respectively. A second terminal of transistor 106 is coupled to ground and the gate of transistor 106 is coupled to the clock signal 108. Although FIG. 1 illustrates an OR circuit, it should be noted that the evaluation transistors can be configured to form any logic circuit as desired by the circuit developer.
The conventional dynamic wide OR circuit 100 operates in two phases, namely, a precharge phase and an evaluation phase. During the precharge phase the clock signal 108 is LOW. Hence, transistor 106 is OFF and the precharge transistor 102 is ON, which allows current to flow from VDD to the internal dynamic node 110. As a result, a precharge is provided to the internal dynamic node 110, which goes HIGH. Because transistor 106 is OFF, the internal dynamic node 110 stays high during the precharge phase regardless of the state of the evaluation transistors 104a-104c. 
During the evaluation phase the clock signal 108 is HIGH. Hence, transistor 106 is ON and the precharge transistor 102 is OFF, which allows current to flow from the internal dynamic node 110 to ground based on the state of the evaluation transistors 104a-104c. The state of each evaluation transistor 104a-104c depends on the state of the input In0, In1, and In2 coupled to the gate of the particular evaluation transistor 104a-104c. As can be seen in the example of FIG. 1, when the input In0, In1, and In2 of any evaluation transistor 104a-104c is HIGH, the evaluation transistor 104a-104c turns ON and allows current to flow from the internal dynamic node 110 to ground through transistor 106. As a result, the output 112 will be LOW.
However, when all the inputs In0, In1, and In2 of the evaluation transistors 104a-104c are LOW, all the evaluation transistors 104a-104c are OFF and the internal dynamic node 110 is allowed to stay HIGH, resulting in a HIGH at the output 112. Unfortunately, the evaluation transistors 104a-104c leak. That is, each evaluation transistor 104a-104c allows a small amount of leakage current to flow to ground through transistor 106 when the evaluation transistor 104a-104c is OFF. Thus, when all the inputs In0, In1, and In2 of the evaluation transistors 104a-104c are LOW, a leakage current is still allowed to flow from the internal dynamic node 110 to ground though transistor 106. Thus, the voltage on the internal dynamic node 110 falls over time.
To combat the leakage current, keeper circuits 114 are utilized. The conventional keeper circuit 114 includes an inverter 118 having an input coupled to the internal dynamic node 110 and an output coupled to the gate of a keeper transistor 116. The keeper transistor 116 includes a first terminal coupled to VDD and a second terminal coupled to the internal dynamic node 110.
The keeper circuit 114 is primarily utilized to address leakage by keeping the internal dynamic node 110 HIGH when all the evaluation transistors 104a-104c are OFF. In particular, when the internal dynamic node 110 is HIGH, the input of the inverter 118 is HIGH, resulting in a LOW at the output of the inverter 118. The LOW at the output of the inverter 118 turns ON the keeper transistor 116, which allows current to flow into the internal dynamic node 110 from VDD.
On the other hand, when the internal dynamic node is LOW, because of an evaluation transistor 104a-104c being ON, the keeper circuit 114 turns OFF. Specifically, when the internal dynamic node 110 is LOW, the input of the inverter 118 is LOW, resulting in a HIGH at the output of the inverter 118. The HIGH at the output of the inverter 118 turns OFF the keeper transistor 116, which prevents current from flowing into the internal dynamic node 110 from VDD.
The leakage current is proportional to the size and number of evaluation devices 104a-104c present in the circuit. Hence, the size of the keeper transistor 116 is selected based on the size and number of evaluation devices 104a-104c present in the circuit, generally, at the worst case for leakage for expected process, voltage, and temperature. It should be noted that the keeper transistor 116 cannot be made arbitrarily large because the keeper transistor circuit 114 will adversely affect evaluation performance if the keeper transistor 116 is too large. In particular, if the keeper transistor 116 is too large, the keeper transistor 116 will try to keep the internal dynamic node 110 HIGH when the evaluation transistors attempt to discharge the internal dynamic node 110. As a result, the evaluation time can be increased and/or the value of the precharged internal dynamic node 110 may not change when an evaluation transistor is ON.
Unfortunately, this also imposes a limit on the number of evaluation devices that can be included in a conventional dynamic circuit. Increasing the number of evaluation transistors in a dynamic circuit increases the amount of leakage current proportionally. As a result, larger keeper transistors 116 are required. However, at some point, the size of keeper transistor 116 becomes too large for a single evaluation transistor 1041-104c to overcome and pull the internal dynamic node 110 LOW. This point becomes the limit to the number of evaluation devices that can be included in the dynamic circuit. Thus, the size of the keeper transistor is conventionally selected based on this limit and the worst-case leakage corner. It is desirable to remove this constraint from the design.
In view of the foregoing, there is a need for a keeper circuit design that allows the effective size of the keeper transistor to be changed based on the individual properties of the chip. The keeper circuits should adjust the effective keeper transistor size based on the requirements of the overall circuit, such as electrical characteristics of the transistors utilized in the circuit. As a result, larger dynamic circuits could be utilized, potentially improving the speed of the microprocessor itself.